1. Field of the Invention
The invention relates to a communicating apparatus for communicating with a plurality of communication control units which are cascade connected.
2. Related Background Art
Hitherto, a serial communication system has been proposed as means for allowing two microprocessors having a plurality of management targets to mutually exchange internal data possessed with respect to own items which are managed by the microprocessor itself.
As such a kind of serial communication system, there has been known a system such that one of microprocessors time-sequentially transmits binary data in accordance with a predetermined procedure onto one or two data lines which are mutually connected for transmission and reception, while the other microprocessor time-sequentially receives the binary data and executes a predetermined arithmetic operating process as necessary by an internal program and an arithmetic operation result is stored into a memory.
However, at present, a serial communication system of a format shown in FIG. 9 has also been proposed. According to the serial communication system, a communication controller 101, a communication IC 103 to which a plurality of sensors 102, . . . are connected, and a communication IC 106 to which a motor driver 105 to drive a motor 104 is connected are cascade-connected through one signal line composed of total four lines of +5V serving as a power supplying line, a GND, a sync clock line, and a data line for serial communication.
In case of providing such a serial communication system into an image forming device such as a copying apparatus or the like and using it, as shown in FIG. 10, the communication controller 101 connected to a control unit of the image forming device and a number of communication ICs 108 to 111 to which sensors 112 to 115 arranged at proper positions in the device are connected through one signal line, thereby performing a transmission/reception communication between the communication controller 101 and each of the communication ICs 108 to 111. In this case, by designating peculiar addresses (address 0, address 1, address 2, . . . ) to the communication ICs irrespective of the arranging positions of the communication ICs 108 to 111 in the device, the transmission/reception communication is executed between each of the communication ICs 108 to 111 of each address and the communication controller 101. As mentioned above, since the data communication is executed by performing the address designation by the serial communication, when communications with a plurality of addresses are simultaneously requested, a delay occurs in the data communication. On the other hand, in a communication in the image forming device, a portion where a delay of the data communication must not be caused and a portion where the data communication may be delayed exists. Therefore, by raising priorities of communications in accordance with the order from the small communication address (for instance, address 0 is set to the highest priority and the priorities are sequentially allocated in accordance with the order of address 1, address 2, . . . ) and by connecting those communication ICs 108 to 111 to the communication controller 101, the communication IC (in this case, the communication IC 108) in which the delay is not permitted mostly is designated to the highest priority and the communication is executed.
In such a serial communication system, by sequentially checking an abnormality of the communication ICs in accordance with the order from the small address number on the basis of a flowchart shown in FIG. 11, a disconnection of the signal line, a failure of the communication IC, or the like, namely, a disconnected portion or a failed portion is detected.
In other words, first in step S51, the number (M) of connection addresses (for example, 4) is set. In step S52, an address number (n) is set to "0". In step S53, the communication controller 101 transmits abnormality diagnosis check data to the communication IC 108 of address 0 synchronously with a clock pulse train. In step S54, the abnormality diagnosis check data is returned from the communication IC 108. The communication controller 101 receives the data and writes its contents into an internal register. In step S55, a check is made to see if the reception data stored in the internal register of the communication IC 108 and the transmission data from the communication controller 101 are the same. When they are equal, it is determined that an abnormality such as disconnection or the like doesn't occur between the communication controller 101 and the communication IC 108 of address 0. Step S56 follows and a check is made to see whether the address number (n) is equal to or larger than (M-1) or not. If NO, namely, when the address number (n) is smaller than (M-1), the address (n) is increased by only "1" (step S57). The processing routine is returned to step S53 and an abnormality diagnosis check similar to that mentioned above is subsequently executed with respect to address 1. If YES in step S56, namely, when it is decided that an abnormality such as disconnection or the like doesn't occur between all of the communication ICs 108 to 111 and the communication controller 101, step S58 follows. The end of abnormality diagnosis check is notified and the processes are finished.
For example, as shown in FIG. 10, when an abnormality such as disconnection or the like occurs between the communication IC 109 of address 1 and the communication IC 110 of address 2, although the communication controller 101 has transmitted the abnormality diagnosis check data to the communication IC 110 of address 2 in step S53, the communication controller 101 cannot receive the abnormality diagnosis check data which is returned from the communication IC 110. Therefore, the transmission data from the communication controller 101 and the storage data (reception data) stored in the internal register of the communication controller 101 are different. In this case, consequently, the answer in step S55 in FIG. 11 is NO. Step S59 follows and an error flag is made active, thereby showing the occurrence of an error. In step S60, a disconnected address (in this case, address 2) in which a failure such as disconnection or the like occurred is notified. The end of check is notified in step S58 and the processes are finished. In this case, as for an abnormality diagnosis of the communication IC 111 of address 3, the presence or absence of the abnormality can be discriminated by correcting the abnormality of the communication IC 109 of address 2 and again executing the foregoing abnormality diagnosis after that.
By executing such an abnormality diagnosis, not only the disconnection of the signal line but also the location of the disconnection or the failed communication IC can be easily and promptly known. An erroneous connection at the time of assembly of the system can be avoided. A countermeasure for repair in case of disconnection can be promptly taken.
In the above conventional technique, the communication ICs 108 to 111 and the communication controller 101 are sequentially connected in accordance with the order from the small address. However, in case of actually assembling them into the apparatus, the communication IC having a high priority is not always arranged on this side. As shown in FIG. 12, for instance, there is also a case where the communication ICs are connected to the communication controller 101 in accordance with the order of address 1, address 2, address 0, and address 3.
In the conventional abnormality diagnosing method, however, as shown in FIG. 12, even in the case where the communication controller 101 and the communication ICs 108 to 111 are cascade connected, the abnormality diagnoses are sequentially performed in accordance with the order from the small address number. Therefore, when an abnormality occurs between the communication controller 101 and the communication IC 108 of address 0, the abnormality diagnosing program is finished at a time point when the abnormality is detected with respect to the communication IC 108 and the abnormality diagnoses are not executed for the communication ICs 109 to 111. That is, in this case, although the occurrence of the abnormality between the communication IC 108 of address 0 and the communication controller 101 can be promptly detected, since the communication IC 109 of address 1 and the communication IC 110 of address 2 exist between the communication controller 101 and the communication IC 108 of address 0, it is impossible to determine in which one of the three communication ICs 108 to 110 a cause of the occurrence of the abnormality exists or at which position on the signal line connected to the communication controller 101 the disconnection or the like occurred. That is, the conventional method of sequentially performing the abnormality diagnoses in accordance with the order from the small address has problems such that the position where the abnormality occurred cannot be specified in dependence on a connecting situation of each of the communication ICs 108 to 111 to the communication controller 101 and a countermeasure cannot be promptly taken for the occurrence of the abnormality.